Driver Output Enable Timing Register
DE_ASSERTION_TIME | Driver Enable Assertion Time This field controls the amount of time (in terms of number of SCLK periods) between the assertion of rising edge of DE signal to serial transmit enable. Any data in transmit buffer, will start on UART_TX signal after the transmit enable. |
DE_DE_ASSERTION_TIME | Driver Enable Deassertion Time This field controls the amount of time (in terms of number of SCLK periods) between the end of the stop bit on the UART_TX signal to the falling edge of DE signal. |